The disclosed concepts relate to a memory device and a method of manufacturing the same and, more particularly, to a memory device having a stacked cross-point array structure and a method of manufacturing the same.
Since there is a growing trend to make electronic products lightweight, thin, and small-sized, the demand for highly-integrated semiconductor devices has increased. Also, a memory device having a stacked cross-point array structure in which a memory cell is located at an intersection between two electrodes crossing each other has been proposed. However, due to the increased need for the downscaling of a memory device having a stacked cross-point structure, it is necessary to reduce sizes of all layers included in the memory device. However, by reducing the size of the memory device, a variety of defects can occur during a process of manufacturing the memory device, thereby deteriorating reliability of the memory device, and reducing mass productivity.